RomRaider

The Idle switch is at Byte 62( based on Logger definition) ,so i go to the routine located at 62nd ?

yes, index 0x62 - idle mode, neutral and some others

I got a question.
My ecm should have a brake switch entry (A8DH200Z 32bit STI IX EDM).
The SSM parameter doesn't react when logging "brake switch".
According to my wiring and the ECM pinout, the wire is present.
When i analyse the 6A SSM subroutine (Stop Light Switch is the 4th parameter), i don't find it.
I have logged many potential RAM adresses to see if they react when i brake but it's unsuccessfull.
So I suppose the code doesn't allocate a RAM space for the brake information but the CPU still have this physical entry.
So the CPU should react according to this I/O port and allocate a RAM address to store a bit value (0 or 1). But we can't logg this RAM sections (From FFFFBFA0).
So how to find it?
And how to link on SH7058 the physical entry to an I/O port RAM result then to a loggable RAM parameter.
Thanks



ROM:0004689E SUB_SSM_UNKNOWN6A: ; DATA XREF: ROM:0004D2ACo
ROM:0004689E sts.l pr, @-r15
ROM:000468A0 mov.l off_46980, r3 ; sub_1692A
ROM:000468A2 add #-4, r15
ROM:000468A4 jsr @r3 ; sub_1692A
ROM:000468A6 nop
ROM:000468A8 mov r0, r4
ROM:000468AA mov r15, r2
ROM:000468AC mov #0, r3
ROM:000468AE extu.b r4, r0
ROM:000468B0 mov.b r3, @r2
ROM:000468B2 cmp/eq #1, r0
ROM:000468B4 bf/s loc_468C2
ROM:000468B6 nop
ROM:000468B8 mov r15, r2
ROM:000468BA mov.b @r2, r0
ROM:000468BC or #2, r0
ROM:000468BE bra loc_468CA
ROM:000468C0 mov.b r0, @r2
ROM:000468C2 ; ---------------------------------------------------------------------------
ROM:000468C2
ROM:000468C2 loc_468C2: ; CODE XREF: SUB_SSM_UNKNOWN6A+16j
ROM:000468C2 mov r15, r1
ROM:000468C4 mov.b @r1, r0
ROM:000468C6 and #h'FD, r0
ROM:000468C8 mov.b r0, @r1
ROM:000468CA
ROM:000468CA loc_468CA: ; CODE XREF: SUB_SSM_UNKNOWN6A+20j
ROM:000468CA mov r15, r0
ROM:000468CC mov.b @r0, r0
ROM:000468CE add #4, r15
ROM:000468D0 lds.l @r15+, pr
ROM:000468D2 rts
ROM:000468D4 nop



sub_1692A: ; CODE XREF: SUB_SSM_UNKNOWN6A+6p
ROM:0001692A ; DATA XREF: SUB_SSM_UNKNOWN6A+2o ...
ROM:0001692A rts
ROM:0001692C mov #0, r0

That parameter relates to the TCM. You should be looking at S67 Brake Switch, byte 0x121 bit 3.

Are you using an old version of defs and RomRaider? The latest version of RR will sort switches and display only those which your ECU supports.

I have updated my defs and i test again. Here's the SSM 121. The test on clutch is done but nothing about Brake switch 2!

UB_SSM_SWITCH121: ; DATA XREF: ROM:0004D588o
ROM:0004718E sts.l pr, @-r15
ROM:00047190 mov.l off_47360, r3 ; Sub_Extract_clutch
ROM:00047192 add #-h'1C, r15
ROM:00047194 jsr @r3 ; Sub_Extract_clutch
ROM:00047196 nop
ROM:00047198 mov.l off_47364, r3 ; sub_1774C
ROM:0004719A mov r15, r1
ROM:0004719C add #h'14, r1
ROM:0004719E jsr @r3 ; sub_1774C
ROM:000471A0 mov.b r0, @r1
ROM:000471A2 mov r15, r2
ROM:000471A4 mov.l off_47368, r3 ; sub_17738
ROM:000471A6 add #h'10, r2
ROM:000471A8 jsr @r3 ; sub_17738
ROM:000471AA mov.b r0, @r2
ROM:000471AC mov.l off_4736C, r3 ; sub_1773C
ROM:000471AE jsr @r3 ; sub_1773C
ROM:000471B0 mov.b r0, @(h'C,r15)
ROM:000471B2 mov.l off_47370, r3 ; sub_17744
ROM:000471B4 jsr @r3 ; sub_17744
ROM:000471B6 mov.b r0, @(8,r15)
ROM:000471B8 mov.l off_47374, r3 ; sub_17754
ROM:000471BA jsr @r3 ; sub_17754
ROM:000471BC mov.b r0, @(4,r15)
ROM:000471BE mov.l off_47378, r3 ; sub_17734
ROM:000471C0 jsr @r3 ; sub_17734
ROM:000471C2 mov.b r0, @r15
ROM:000471C4 mov r0, r4
ROM:000471C6 mov r15, r2
ROM:000471C8 add #h'18, r2
ROM:000471CA mov #0, r3
ROM:000471CC mov.b r3, @r2
ROM:000471CE mov #h'14, r0
ROM:000471D0 mov.b @(r0,r15), r0
ROM:000471D2 extu.b r0, r0
ROM:000471D4 cmp/eq #1, r0
ROM:000471D6 bf/s loc_471E6
ROM:000471D8 nop
ROM:000471DA mov r15, r2
ROM:000471DC add #h'18, r2
ROM:000471DE mov.b @r2, r0
ROM:000471E0 or #h'80, r0
ROM:000471E2 bra loc_471F0
ROM:000471E4 mov.b r0, @r2
ROM:000471E6 ; ---------------------------------------------------------------------------
ROM:000471E6
ROM:000471E6 loc_471E6: ; CODE XREF: SUB_SSM_SWITCH121+48j
ROM:000471E6 mov r15, r1
ROM:000471E8 add #h'18, r1
ROM:000471EA mov.b @r1, r0
ROM:000471EC and #h'7F, r0
ROM:000471EE mov.b r0, @r1
ROM:000471F0
ROM:000471F0 loc_471F0: ; CODE XREF: SUB_SSM_SWITCH121+54j
ROM:000471F0 mov #h'10, r0
ROM:000471F2 mov.b @(r0,r15), r0
ROM:000471F4 extu.b r0, r0
ROM:000471F6 cmp/eq #1, r0
ROM:000471F8 bf/s loc_47208
ROM:000471FA nop
ROM:000471FC mov r15, r2
ROM:000471FE add #h'18, r2
ROM:00047200 mov.b @r2, r0
ROM:00047202 or #h'40, r0
ROM:00047204 bra loc_47212
ROM:00047206 mov.b r0, @r2
ROM:00047208 ; ---------------------------------------------------------------------------
ROM:00047208
ROM:00047208 loc_47208: ; CODE XREF: SUB_SSM_SWITCH121+6Aj
ROM:00047208 mov r15, r1
ROM:0004720A add #h'18, r1
ROM:0004720C mov.b @r1, r0
ROM:0004720E and #h'BF, r0
ROM:00047210 mov.b r0, @r1
ROM:00047212
ROM:00047212 loc_47212: ; CODE XREF: SUB_SSM_SWITCH121+76j
ROM:00047212 mov.b @(h'C,r15), r0
ROM:00047214 extu.b r0, r0
ROM:00047216 cmp/eq #1, r0
ROM:00047218 bf/s loc_47228
ROM:0004721A nop
ROM:0004721C mov r15, r2
ROM:0004721E add #h'18, r2
ROM:00047220 mov.b @r2, r0
ROM:00047222 or #h'20, r0
ROM:00047224 bra loc_47232
ROM:00047226 mov.b r0, @r2
ROM:00047228 ; ---------------------------------------------------------------------------
ROM:00047228
ROM:00047228 loc_47228: ; CODE XREF: SUB_SSM_SWITCH121+8Aj
ROM:00047228 mov r15, r1
ROM:0004722A add #h'18, r1
ROM:0004722C mov.b @r1, r0
ROM:0004722E and #h'DF, r0
ROM:00047230 mov.b r0, @r1
ROM:00047232
ROM:00047232 loc_47232: ; CODE XREF: SUB_SSM_SWITCH121+96j
ROM:00047232 mov.b @(8,r15), r0
ROM:00047234 extu.b r0, r0
ROM:00047236 cmp/eq #1, r0
ROM:00047238 bf/s loc_47248
ROM:0004723A nop
ROM:0004723C mov r15, r2
ROM:0004723E add #h'18, r2
ROM:00047240 mov.b @r2, r0
ROM:00047242 or #h'10, r0
ROM:00047244 bra loc_47252
ROM:00047246 mov.b r0, @r2
ROM:00047248 ; ---------------------------------------------------------------------------
ROM:00047248
ROM:00047248 loc_47248: ; CODE XREF: SUB_SSM_SWITCH121+AAj
ROM:00047248 mov r15, r1
ROM:0004724A add #h'18, r1
ROM:0004724C mov.b @r1, r0
ROM:0004724E and #h'EF, r0
ROM:00047250 mov.b r0, @r1
ROM:00047252
ROM:00047252 loc_47252: ; CODE XREF: SUB_SSM_SWITCH121+B6j
ROM:00047252 mov.b @(4,r15), r0
ROM:00047254 extu.b r0, r0
ROM:00047256 cmp/eq #1, r0
ROM:00047258 bf/s loc_47268
ROM:0004725A nop
ROM:0004725C mov r15, r2
ROM:0004725E add #h'18, r2
ROM:00047260 mov.b @r2, r0
ROM:00047262 or #8, r0
ROM:00047264 bra loc_47272
ROM:00047266 mov.b r0, @r2
ROM:00047268 ; ---------------------------------------------------------------------------
ROM:00047268
ROM:00047268 loc_47268: ; CODE XREF: SUB_SSM_SWITCH121+CAj
ROM:00047268 mov r15, r1
ROM:0004726A add #h'18, r1
ROM:0004726C mov.b @r1, r0
ROM:0004726E and #h'F7, r0
ROM:00047270 mov.b r0, @r1
ROM:00047272
ROM:00047272 loc_47272: ; CODE XREF: SUB_SSM_SWITCH121+D6j
ROM:00047272 extu.b r4, r0
ROM:00047274 cmp/eq #1, r0
ROM:00047276 bf/s loc_47286
ROM:00047278 nop
ROM:0004727A mov r15, r2
ROM:0004727C add #h'18, r2
ROM:0004727E mov.b @r2, r0
ROM:00047280 or #2, r0
ROM:00047282 bra loc_47290
ROM:00047284 mov.b r0, @r2
ROM:00047286 ; ---------------------------------------------------------------------------
ROM:00047286
ROM:00047286 loc_47286: ; CODE XREF: SUB_SSM_SWITCH121+E8j
ROM:00047286 mov r15, r1
ROM:00047288 add #h'18, r1
ROM:0004728A mov.b @r1, r0
ROM:0004728C and #h'FD, r0
ROM:0004728E mov.b r0, @r1
ROM:00047290
ROM:00047290 loc_47290: ; CODE XREF: SUB_SSM_SWITCH121+F4j
ROM:00047290 mov.b @r15, r0
ROM:00047292 extu.b r0, r0
ROM:00047294 cmp/eq #1, r0
ROM:00047296 bf/s loc_472A6
ROM:00047298 nop
ROM:0004729A mov r15, r2
ROM:0004729C add #h'18, r2
ROM:0004729E mov.b @r2, r0
ROM:000472A0 or #1, r0
ROM:000472A2 bra loc_472B0
ROM:000472A4 mov.b r0, @r2
ROM:000472A6 ; ---------------------------------------------------------------------------
ROM:000472A6
ROM:000472A6 loc_472A6: ; CODE XREF: SUB_SSM_SWITCH121+108j
ROM:000472A6 mov r15, r1
ROM:000472A8 add #h'18, r1
ROM:000472AA mov.b @r1, r0
ROM:000472AC and #h'FE, r0
ROM:000472AE mov.b r0, @r1
ROM:000472B0
ROM:000472B0 loc_472B0: ; CODE XREF: SUB_SSM_SWITCH121+114j
ROM:000472B0 mov r15, r0
ROM:000472B2 add #h'18, r0
ROM:000472B4 mov.b @r0, r0
ROM:000472B6 add #h'1C, r15
ROM:000472B8 lds.l @r15+, pr
ROM:000472BA rts
ROM:000472BC nop
ROM:000472BC ; End of function SUB_SSM_SWITCH121



Sub_Extract_clutch: ; CODE XREF: sub_162F0+34p
ROM:0001E7BC ; sub_2C2A6+32p ...
ROM:0001E7BC mov.l off_1E7F8, r0 ; RAM_Switch121_Clutch80
ROM:0001E7BE mov.b @r0, r0
ROM:0001E7C0 tst #h'80, r0
ROM:0001E7C2 movt r0
ROM:0001E7C4 add #-1, r0
ROM:0001E7C6 neg r0, r0
ROM:0001E7C8 cmp/eq #1, r0
ROM:0001E7CA movt r0
ROM:0001E7CC rts
ROM:0001E7CE nop



sub_1774C,sub_17738,sub_1773C,sub_17744,sub_17754,sub_17734
rts
mov #0, r0

With the update, there"s no "stop switch".
However, i see there's the "handle switch" but i know for sure there's no entry to the ECM. The "handle switch" parameter doesn't work.

I checked the brake pedal and all the wiring. I confirm it goes from the switch to B135 28 (white/black).

Handle switch indicates right or left hand drive car configuration.

Since you have no brake switch checking code that parameter is not used by the ECU.

Ok but there's no way ti write it?

Write the code to read the input you mean?

You need to know if the IO port is even initialized for reading by the CPU.
You have to find which CPU IO port the brake signal is connected to from the circuit board's wire harness connector.
It may be very difficult to trace the wire harness connector pin to the CPU IO port pin across the circuit board, but if you do then it may be possible to add code.

Ok. And is the opposite work available?
For example with the defog switch. I know the RAM adress and the bit involved.Can i find the port?

Yes you should be able to trace the code back to figure out the source IO port. I have not put much effort into this myself. I've only done the ADC ports.

Could you explain please how you did? With an example please?
The goal is to goback to I/O initial RAM allocation like these we agree?


RAM:FFFFE800 FLASH_FCCS_B: .res.b 1
RAM:FFFFE801 FLASH_FPCS_B: .res.b 1
RAM:FFFFE802 FLASH_FECS_B: .res.b 1
RAM:FFFFE803 .res.b 1
RAM:FFFFE804 FLASH_FKEY_B: .res.b 1
RAM:FFFFE805 FLASH_FMATS_B: .res.b 1
RAM:FFFFE806 FLASH_FTDAR_B: .res.b 1
RAM:FFFFE807 .res.b h'3F9
RAM:FFFFEC00 UBC_UBARH_W: .res.b 2
RAM:FFFFEC02 UBC_UBARL_W: .res.b 2
RAM:FFFFEC04 UBC_UBAMRH_W: .res.b 2
RAM:FFFFEC06 UBC_UBAMRL_W: .res.b 2
RAM:FFFFEC08 UBC_UBBR_W: .res.b 2
RAM:FFFFEC0A UBC_UBCR_W: .res.b 2
RAM:FFFFEC0C .res.b 1
RAM:FFFFEC0D .res.b 1
RAM:FFFFEC0E .res.b 1
RAM:FFFFEC0F .res.b 1
RAM:FFFFEC10 WDT_TCSR_RW__B: .res.b 1
RAM:FFFFEC11 WDT_TCNT_B: .res.b 1
RAM:FFFFEC12 WDT_RSTCSR_W__B:.res.b 1
RAM:FFFFEC13 WDT_RSTCSR_R__B:.res.b 1
RAM:FFFFEC14 SBYCR_B: .res.b 1
RAM:FFFFEC15 .res.b h'B
RAM:FFFFEC20 BSC_BCR1_W: .res.b 2
RAM:FFFFEC22 BSC_BCR2_W: .res.b 2
RAM:FFFFEC24 BSC_WCR_W: .res.b 2
RAM:FFFFEC26 BSC_RAMER_W: .res.b 2
RAM:FFFFEC28 .res.b h'88
RAM:FFFFECB0 DMAC_DMAOR_W: .res.b 2
RAM:FFFFECB2 .res.b h'E
RAM:FFFFECC0 DMAC_SAR0_L: .res.b 4
RAM:FFFFECC4 DMAC_DAR0_L: .res.b 4
RAM:FFFFECC8 DMAC_DMATCR0_L: .res.b 4
RAM:FFFFECCC DMAC_CHCR0_L: .res.b 4
RAM:FFFFECD0 DMAC_SAR1_L: .res.b 4
RAM:FFFFECD4 DMAC_DAR1_L: .res.b 4
RAM:FFFFECD8 DMAC_DMATCR1_L: .res.b 4
RAM:FFFFECDC DMAC_CHCR1_L: .res.b 4
RAM:FFFFECE0 DMAC_SAR2_L: .res.b 4
RAM:FFFFECE4 DMAC_DAR2_L: .res.b 4
RAM:FFFFECE8 DMAC_DMATCR2_L: .res.b 4
RAM:FFFFECEC DMAC_CHCR2_L: .res.b 4
RAM:FFFFECF0 DMAC_SAR3_L: .res.b 4
RAM:FFFFECF4 DMAC_DAR3_L: .res.b 4
RAM:FFFFECF8 DMAC_DMATCR3_L: .res.b 4
RAM:FFFFECFC DMAC_CHCR3_L: .res.b 4
RAM:FFFFED00 IPRA_W: .res.b 2
RAM:FFFFED02 IPRB_W: .res.b 2
RAM:FFFFED04 IPRC_W: .res.b 2
RAM:FFFFED06 IPRD_W: .res.b 2
RAM:FFFFED08 IPRE_W: .res.b 2
RAM:FFFFED0A IPRF_W: .res.b 2
RAM:FFFFED0C IPRG_W: .res.b 2
RAM:FFFFED0E IPRH_W: .res.b 2
RAM:FFFFED10 IPRI_W: .res.b 2
RAM:FFFFED12 IPRJ_W: .res.b 2
RAM:FFFFED14 IPRK_W: .res.b 2
RAM:FFFFED16 IPRL_W: .res.b 2
RAM:FFFFED18 ICR_W: .res.b 2
RAM:FFFFED1A ISR_W: .res.b 2
RAM:FFFFED1C .res.b h'2E4
RAM:FFFFF000 SCI_SMR0_B: .res.b 1
RAM:FFFFF001 SCI_BRR0_B: .res.b 1
RAM:FFFFF002 SCI_SCR0_B: .res.b 1
RAM:FFFFF003 SCI_TDR0_B: .res.b 1
RAM:FFFFF004 SCI_SSR0_B: .res.b 1
RAM:FFFFF005 SCI_RDR0_B: .res.b 1
RAM:FFFFF006 SCI_SDCR0_B: .res.b 1
RAM:FFFFF007 .res.b 1
RAM:FFFFF008 SCI_SMR1_B: .res.b 1
RAM:FFFFF009 SCI_BRR1_B: .res.b 1
RAM:FFFFF00A SCI_SCR1_B: .res.b 1
RAM:FFFFF00B SCI_TDR1_B: .res.b 1
RAM:FFFFF00C SCI_SSR1_B: .res.b 1
RAM:FFFFF00D SCI_RDR1_B: .res.b 1
RAM:FFFFF00E SCI_SDCR1_B: .res.b 1
RAM:FFFFF00F .res.b 1
RAM:FFFFF010 SCI_SMR2_B: .res.b 1
RAM:FFFFF011 SCI_BRR2_B: .res.b 1
RAM:FFFFF012 SCI_SCR2_B: .res.b 1
RAM:FFFFF013 SCI_TDR2_B: .res.b 1
RAM:FFFFF014 SCI_SSR2_B: .res.b 1
RAM:FFFFF015 SCI_RDR2_B: .res.b 1
RAM:FFFFF016 SCI_SDCR2_B: .res.b 1
RAM:FFFFF017 .res.b 1
RAM:FFFFF018 SCI_SMR3_B: .res.b 1
RAM:FFFFF019 SCI_BRR3_B: .res.b 1
RAM:FFFFF01A SCI_SCR3_B: .res.b 1
RAM:FFFFF01B SCI_TDR3_B: .res.b 1
RAM:FFFFF01C SCI_SSR3_B: .res.b 1
RAM:FFFFF01D SCI_RDR3_B: .res.b 1
RAM:FFFFF01E SCI_SDCR3_B: .res.b 1
RAM:FFFFF01F .res.b 1
RAM:FFFFF020 SCI_SMR4_B: .res.b 1
RAM:FFFFF021 SCI_BRR4_B: .res.b 1
RAM:FFFFF022 SCI_SCR4_B: .res.b 1
RAM:FFFFF023 SCI_TDR4_B: .res.b 1
RAM:FFFFF024 SCI_SSR4_B: .res.b 1
RAM:FFFFF025 SCI_RDR4_B: .res.b 1
RAM:FFFFF026 SCI_SDCR4_B: .res.b 1
RAM:FFFFF027 .res.b h'3D9
RAM:FFFFF400 ATUII_TSTR2_B: .res.b 1
RAM:FFFFF401 ATUII_TSTR1_B: .res.b 1
RAM:FFFFF402 ATUII_TSTR3_B: .res.b 2
RAM:FFFFF404 ATUII_PSCR1_B: .res.b 2
RAM:FFFFF406 ATUII_PSCR2_B: .res.b 2
RAM:FFFFF408 ATUII_PSCR3_B: .res.b 2
RAM:FFFFF40A ATUII_PSCR4_B: .res.b 1
RAM:FFFFF40B .res.b h'15
RAM:FFFFF420 ATUII_ICR0DH_W: .res.b 2
RAM:FFFFF422 ATUII_ICR0DL_W: .res.b 2
RAM:FFFFF424 ATUII_ITVRR1_B: .res.b 2
RAM:FFFFF426 ATUII_ITVRR2A_B:.res.b 2
RAM:FFFFF428 ATUII_ITVRR2B_B:.res.b 2
RAM:FFFFF42A ATUII_TIOR0_B: .res.b 2
RAM:FFFFF42C ATUII_TSR0_W: .res.b 2
RAM:FFFFF42E ATUII_TIER0_W: .res.b 2
RAM:FFFFF430 ATUII_TCNT0H_W: .res.b 2
RAM:FFFFF432 ATUII_TCNT0L_W: .res.b 2
RAM:FFFFF434 ATUII_ICR0AH_W: .res.b 2
RAM:FFFFF436 ATUII_ICR0AL_W: .res.b 2
RAM:FFFFF438 ATUII_ICR0BH_W: .res.b 2
RAM:FFFFF43A ATUII_ICR0BL_W: .res.b 2
RAM:FFFFF43C ATUII_ICR0CH_W: .res.b 2
RAM:FFFFF43E ATUII_ICR0CL_W: .res.b 2
RAM:FFFFF440 ATUII_TCNT1A_W: .res.b 2
RAM:FFFFF442 ATUII_TCNT1B_W: .res.b 2
RAM:FFFFF444 ATUII_GR1A_W: .res.b 2 ; DATA XREF: ROM:00011EC0o
RAM:FFFFF446 ATUII_GR1B_W: .res.b 2 ; DATA XREF: ROM:00011ECCo
RAM:FFFFF448 ATUII_GR1C_W: .res.b 2 ; DATA XREF: ROM:00011ED8o
RAM:FFFFF44A ATUII_GR1D_W: .res.b 2 ; DATA XREF: ROM:00011EE4o
RAM:FFFFF44C ATUII_GR1E_W: .res.b 2
RAM:FFFFF44E ATUII_GR1F_W: .res.b 2
RAM:FFFFF450 ATUII_GR1G_W: .res.b 2
RAM:FFFFF452 ATUII_GR1H_W: .res.b 2
RAM:FFFFF454 ATUII_OCR1_W: .res.b 2
RAM:FFFFF456 ATUII_OSBR1_W: .res.b 2
RAM:FFFFF458 ATUII_TIOR1B_B: .res.b 1
RAM:FFFFF459 ATUII_TIOR1A_B: .res.b 1
RAM:FFFFF45A ATUII_TIOR1D_B: .res.b 1
RAM:FFFFF45B ATUII_TIOR1C_B: .res.b 1
RAM:FFFFF45C ATUII_TCR1B_B: .res.b 1
RAM:FFFFF45D ATUII_TCR1A_B: .res.b 1
RAM:FFFFF45E ATUII_TSR1A_W: .res.b 2
RAM:FFFFF460 ATUII_TSR1B_W: .res.b 2
RAM:FFFFF462 ATUII_TIER1A_W: .res.b 2
RAM:FFFFF464 ATUII_TIER1B_W: .res.b 2
RAM:FFFFF466 ATUII_TRGMDR_B: .res.b 1
RAM:FFFFF467 .res.b h'19
RAM:FFFFF480 ATUII_TSR3_W: .res.b 2
RAM:FFFFF482 ATUII_TIER3_W: .res.b 2
RAM:FFFFF484 ATUII_TMDR_B: .res.b 1
RAM:FFFFF485 .res.b h'1B
RAM:FFFFF4A0 ATUII_TCNT3_W: .res.b 2
RAM:FFFFF4A2 ATUII_TGR3A_W: .res.b 2
RAM:FFFFF4A4 ATUII_GR3B_W: .res.b 2
RAM:FFFFF4A6 ATUII_GR3C_W: .res.b 2
RAM:FFFFF4A8 ATUII_GR3D_W: .res.b 2
RAM:FFFFF4AA ATUII_TIOR3B_B: .res.b 1
RAM:FFFFF4AB ATUII_TIOR3A_B: .res.b 1
RAM:FFFFF4AC ATUII_TCR3_B: .res.b 1
RAM:FFFFF4AD .res.b h'13
RAM:FFFFF4C0 ATUII_TCNT4_W: .res.b 2
RAM:FFFFF4C2 ATUII_GR4A_W: .res.b 2
RAM:FFFFF4C4 ATUII_GR4B_W: .res.b 2
RAM:FFFFF4C6 ATUII_GR4C_W: .res.b 2
RAM:FFFFF4C8 ATUII_GR4D_W: .res.b 2
RAM:FFFFF4CA ATUII_TIOR4B_B: .res.b 1
RAM:FFFFF4CB ATUII_TIOR4A_B: .res.b 1
RAM:FFFFF4CC ATUII_TCR4_W: .res.b 1
RAM:FFFFF4CD .res.b h'13
RAM:FFFFF4E0 ATUII_TCNT5_W: .res.b 2
RAM:FFFFF4E2 ATUII_GR5A_W: .res.b 2
RAM:FFFFF4E4 ATUII_GR5B_W: .res.b 2
RAM:FFFFF4E6 ATUII_GR5C_W: .res.b 2
RAM:FFFFF4E8 ATUII_GR5D_W: .res.b 2
RAM:FFFFF4EA ATUII_TIOR5B_B: .res.b 1
RAM:FFFFF4EB ATUII_TIOR5A_B: .res.b 1
RAM:FFFFF4EC ATUII_TCR5_W: .res.b 1
RAM:FFFFF4ED .res.b h'13
RAM:FFFFF500 ATUII_TCNT6A_W: .res.b 2
RAM:FFFFF502 ATUII_TCNT6B_W: .res.b 2
RAM:FFFFF504 ATUII_TCNT6C_W: .res.b 2
RAM:FFFFF506 ATUII_TCNT6D_W: .res.b 2
RAM:FFFFF508 ATUII_CYLR6A_W: .res.b 2
RAM:FFFFF50A ATUII_CYLR6B_W: .res.b 2
RAM:FFFFF50C ATUII_CYLR6C_W: .res.b 2
RAM:FFFFF50E ATUII_CYLR6D_W: .res.b 2
RAM:FFFFF510 ATUII_BFR6A_W: .res.b 2
RAM:FFFFF512 ATUII_BFR6B_W: .res.b 2
RAM:FFFFF514 ATUII_BFR6C_W: .res.b 2
RAM:FFFFF516 ATUII_BFR6D_W: .res.b 2
RAM:FFFFF518 ATUII_DTR6A_W: .res.b 2
RAM:FFFFF51A ATUII_DTR6B_W: .res.b 2
RAM:FFFFF51C ATUII_DTR6C_W: .res.b 2
RAM:FFFFF51E ATUII_DTR6D_W: .res.b 2
RAM:FFFFF520 ATUII_TCR6B_B: .res.b 1
RAM:FFFFF521 ATUII_TCR6A_B: .res.b 1
RAM:FFFFF522 ATUII_TSR6_W: .res.b 2
RAM:FFFFF524 ATUII_TIER6_W: .res.b 2
RAM:FFFFF526 ATUII_PMDR6_B: .res.b 1
RAM:FFFFF527 .res.b h'59
RAM:FFFFF580 ATUII_TCNT7A_W: .res.b 2
RAM:FFFFF582 ATUII_TCNT7B_W: .res.b 2
RAM:FFFFF584 ATUII_TCNT7C_W: .res.b 2
RAM:FFFFF586 ATUII_TCNT7D_W: .res.b 2
RAM:FFFFF588 ATUII_CYLR7A_W: .res.b 2
RAM:FFFFF58A ATUII_CYLR7B_W: .res.b 2
RAM:FFFFF58C ATUII_CYLR7C_W: .res.b 2
RAM:FFFFF58E ATUII_CYLR7D_W: .res.b 2
RAM:FFFFF590 ATUII_BFR7A_W: .res.b 2
RAM:FFFFF592 ATUII_BFR7B_W: .res.b 2
RAM:FFFFF594 ATUII_BFR7C_W: .res.b 2
RAM:FFFFF596 ATUII_BFR7D_W: .res.b 2
RAM:FFFFF598 ATUII_DTR7A_W: .res.b 2
RAM:FFFFF59A ATUII_DTR7B_W: .res.b 2
RAM:FFFFF59C ATUII_DTR7C_W: .res.b 2
RAM:FFFFF59E ATUII_DTR7D_W: .res.b 2
RAM:FFFFF5A0 ATUII_TCR7B_B: .res.b 1
RAM:FFFFF5A1 ATUII_TCR7A_B: .res.b 1
RAM:FFFFF5A2 ATUII_TSR7_W: .res.b 2
RAM:FFFFF5A4 ATUII_TIER7_W: .res.b 2
RAM:FFFFF5A6 .res.b h'1A
RAM:FFFFF5C0 ATUII_TCNT11_W: .res.b 2
RAM:FFFFF5C2 ATUII_GR11A_W: .res.b 2
RAM:FFFFF5C4 ATUII_GR11B_W: .res.b 2
RAM:FFFFF5C6 ATUII_TIOR11_B: .res.b 2
RAM:FFFFF5C8 ATUII_TCR11_B: .res.b 2
RAM:FFFFF5CA ATUII_TSR11_W: .res.b 2
RAM:FFFFF5CC ATUII_TIER11_W: .res.b 2
RAM:FFFFF5CE .res.b h'32
RAM:FFFFF600 ATUII_TCNT2A_W: .res.b 2
RAM:FFFFF602 ATUII_TCNT2B_W: .res.b 2 ; DATA XREF: ROM:00011EF8o
RAM:FFFFF602 ; ROM:00011F10o ...
RAM:FFFFF604 ATUII_GR2A_W: .res.b 2 ; DATA XREF: ROM:00011EF4o
RAM:FFFFF606 ATUII_GR2B_W: .res.b 2 ; DATA XREF: ROM:00011F0Co
RAM:FFFFF608 ATUII_GR2C_W: .res.b 2 ; DATA XREF: ROM:00011F24o
RAM:FFFFF60A ATUII_GR2D_W: .res.b 2 ; DATA XREF: ROM:00011F3Co
RAM:FFFFF60C ATUII_GR2E_W: .res.b 2
RAM:FFFFF60E ATUII_GR2F_W: .res.b 2
RAM:FFFFF610 ATUII_GR2G_W: .res.b 2
RAM:FFFFF612 ATUII_GR2H_W: .res.b 2
RAM:FFFFF614 ATUII_OCR2A_W: .res.b 2 ; DATA XREF: ROM:00011EF0o
RAM:FFFFF616 ATUII_OCR2B_W: .res.b 2 ; DATA XREF: ROM:00011F08o
RAM:FFFFF618 ATUII_OCR2C_W: .res.b 2 ; DATA XREF: ROM:00011F20o
RAM:FFFFF61A ATUII_OCR2D_W: .res.b 2 ; DATA XREF: ROM:00011F38o
RAM:FFFFF61C ATUII_OCR2E_W: .res.b 2
RAM:FFFFF61E ATUII_OCR2F_W: .res.b 2
RAM:FFFFF620 ATUII_OCR2G_W: .res.b 2
RAM:FFFFF622 ATUII_OCR2H_W: .res.b 2
RAM:FFFFF624 ATUII_OSBR2_W: .res.b 2
RAM:FFFFF626 ATUII_TIOR2B_B: .res.b 1
RAM:FFFFF627 ATUII_TIOR2A_B: .res.b 1
RAM:FFFFF628 ATUII_TIOR2D_B: .res.b 1
RAM:FFFFF629 ATUII_TIOR2C_B: .res.b 1
RAM:FFFFF62A ATUII_TCR2B_B: .res.b 1
RAM:FFFFF62B ATUII_TCR2A_B: .res.b 1
RAM:FFFFF62C ATUII_TSR2A_W: .res.b 2
RAM:FFFFF62E ATUII_TSR2B_W: .res.b 2
RAM:FFFFF630 ATUII_TIER2A_W: .res.b 2
RAM:FFFFF632 ATUII_TIER2B_W: .res.b 2
RAM:FFFFF634 .res.b h'C
RAM:FFFFF640 ATUII_DCNT8A_W: .res.b 2 ; DATA XREF: ROM:off_11EBCo
RAM:FFFFF642 ATUII_DNCT8B_W: .res.b 2 ; DATA XREF: ROM:00011EC8o
RAM:FFFFF644 ATUII_DNCT8C_W: .res.b 2 ; DATA XREF: ROM:00011ED4o
RAM:FFFFF646 ATUII_DCNT8D_W: .res.b 2 ; DATA XREF: ROM:00011EE0o
RAM:FFFFF648 ATUII_DCNT8E_W: .res.b 2
RAM:FFFFF64A ATUII_DCNT8F_W: .res.b 2
RAM:FFFFF64C ATUII_DCNT8G_W: .res.b 2
RAM:FFFFF64E ATUII_DCNT8H_W: .res.b 2
RAM:FFFFF650 ATUII_DCNT8I_W: .res.b 2 ; DATA XREF: ROM:ATU_Channel8_Ch2_addresseso
RAM:FFFFF652 ATUII_DCNT8J_W: .res.b 2 ; DATA XREF: ROM:00011F04o
RAM:FFFFF654 ATUII_DCNT8K_W: .res.b 2 ; DATA XREF: ROM:00011F1Co
RAM:FFFFF656 ATUII_DCNT8L_W: .res.b 2 ; DATA XREF: ROM:00011F34o
RAM:FFFFF658 ATUII_DCNT8M_W: .res.b 2
RAM:FFFFF65A ATUII_DCNT8N_W: .res.b 2
RAM:FFFFF65C ATUII_DCNT8O_W: .res.b 2
RAM:FFFFF65E ATUII_DCNT8P_W: .res.b 2
RAM:FFFFF660 ATUII_RLDR8_W: .res.b 2
RAM:FFFFF662 ATUII_TCNR_W: .res.b 2
RAM:FFFFF664 ATUII_OTR_W: .res.b 2
RAM:FFFFF666 ATUII_DSTR_W: .res.b 2 ; DATA XREF: ROM:00011EFCo
RAM:FFFFF666 ; ROM:00011F14o ...
RAM:FFFFF668 ATUII_TCR8_B: .res.b 2
RAM:FFFFF66A ATUII_TSR8_W: .res.b 2
RAM:FFFFF66C ATUII_TIER8_W: .res.b 2
RAM:FFFFF66E ATUII_RLDENR_B: .res.b 1
RAM:FFFFF66F .res.b h'11
RAM:FFFFF680 ATUII_ECNT9A_B: .res.b 2
RAM:FFFFF682 ATUII_ECNT9B_B: .res.b 2
RAM:FFFFF684 ATUII_ECNT9C_B: .res.b 2
RAM:FFFFF686 ATUII_ECNT9D_B: .res.b 2
RAM:FFFFF688 ATUII_ECNT9E_B: .res.b 2
RAM:FFFFF68A ATUII_ECNT9F_B: .res.b 2
RAM:FFFFF68C ATUII_GR9A_B: .res.b 2
RAM:FFFFF68E ATUII_GR9B_B: .res.b 2
RAM:FFFFF690 ATUII_GR9C_B: .res.b 2
RAM:FFFFF692 ATUII_GR9D_B: .res.b 2
RAM:FFFFF694 ATUII_GR9E_B: .res.b 2
RAM:FFFFF696 ATUII_GR9F_B: .res.b 2
RAM:FFFFF698 ATUII_TCR9A_B: .res.b 2
RAM:FFFFF69A ATUII_TCR9B_B: .res.b 2
RAM:FFFFF69C ATUII_TCR9C_B: .res.b 2
RAM:FFFFF69E ATUII_TSR9_W: .res.b 2
RAM:FFFFF6A0 ATUII_TIER9_W: .res.b 2
RAM:FFFFF6A2 .res.b h'1E
RAM:FFFFF6C0 ATUII_TCNT10AH_W:.res.b 2
RAM:FFFFF6C2 ATUII_TCNT10AL_W:.res.b 2
RAM:FFFFF6C4 ATUII_TCNT10B_B:.res.b 2
RAM:FFFFF6C6 ATUII_TCNT10C_W:.res.b 2
RAM:FFFFF6C8 ATUII_TCNT10D_B:.res.b 2
RAM:FFFFF6CA ATUII_TCNT10E_W:.res.b 2
RAM:FFFFF6CC ATUII_TCNT10F_W:.res.b 2
RAM:FFFFF6CE ATUII_TCNT10G_W:.res.b 2
RAM:FFFFF6D0 ATUII_ICR10AH_W:.res.b 2
RAM:FFFFF6D2 ATUII_ICR10AL_W:.res.b 2
RAM:FFFFF6D4 ATUII_OCR10AH_W:.res.b 2
RAM:FFFFF6D6 ATUII_OCR10AL_W:.res.b 2
RAM:FFFFF6D8 ATUII_OCR10B_B: .res.b 2
RAM:FFFFF6DA ATUII_RLD10C_W: .res.b 2
RAM:FFFFF6DC ATUII_GR10G_W: .res.b 2
RAM:FFFFF6DE ATUII_TCNT10H_B:.res.b 2
RAM:FFFFF6E0 ATUII_NCR10_B: .res.b 2
RAM:FFFFF6E2 ATUII_TIOR10_B: .res.b 2
RAM:FFFFF6E4 ATUII_TCR10_B: .res.b 2
RAM:FFFFF6E6 ATUII_TCCLR10_W:.res.b 2
RAM:FFFFF6E8 ATUII_TSR10_W: .res.b 2
RAM:FFFFF6EA ATUII_TIER10_W: .res.b 2
RAM:FFFFF6EC .res.b 1
RAM:FFFFF6ED .res.b 1
RAM:FFFFF6EE .res.b 1
RAM:FFFFF6EF .res.b 1
RAM:FFFFF6F0 .res.b 1
RAM:FFFFF6F1 .res.b 1
RAM:FFFFF6F2 .res.b 1
RAM:FFFFF6F3 .res.b 1
RAM:FFFFF6F4 .res.b 1
RAM:FFFFF6F5 .res.b 1
RAM:FFFFF6F6 .res.b 1
RAM:FFFFF6F7 .res.b 1
RAM:FFFFF6F8 .res.b 1
RAM:FFFFF6F9 .res.b 1
RAM:FFFFF6FA .res.b 1
RAM:FFFFF6FB .res.b 1
RAM:FFFFF6FC .res.b 1
RAM:FFFFF6FD .res.b 1
RAM:FFFFF6FE .res.b 1
RAM:FFFFF6FF .res.b 1
RAM:FFFFF700 APC_POPCRE_B: .res.b 1
RAM:FFFFF701 APC_PULS7SOE_B: .res.b 1
RAM:FFFFF702 .res.b 1
RAM:FFFFF703 .res.b 1
RAM:FFFFF704 .res.b 1
RAM:FFFFF705 .res.b 1
RAM:FFFFF706 .res.b 1
RAM:FFFFF707 .res.b 1
RAM:FFFFF708 SYSCR1_B: .res.b 1
RAM:FFFFF709 .res.b 1
RAM:FFFFF70A SYCSR2__W__W: .res.b 1
RAM:FFFFF70B SYCSR2__R__B: .res.b 1
RAM:FFFFF70C .res.b 1
RAM:FFFFF70D .res.b 1
RAM:FFFFF70E .res.b 1
RAM:FFFFF70F .res.b 1
RAM:FFFFF710 CMSTR_W: .res.b 2
RAM:FFFFF712 CMCSR0_W: .res.b 2
RAM:FFFFF714 CMCNT0_W: .res.b 2
RAM:FFFFF716 CMCOR0_W: .res.b 2
RAM:FFFFF718 CMCSR1_W: .res.b 2
RAM:FFFFF71A CMCNT1_W: .res.b 2
RAM:FFFFF71C CMCOR1_W: .res.b 2
RAM:FFFFF71E .res.b 1
RAM:FFFFF71F .res.b 1
RAM:FFFFF720 PAIOR_W: .res.b 2
RAM:FFFFF722 PACRH_W: .res.b 2
RAM:FFFFF724 PACRL_W: .res.b 2
RAM:FFFFF726 PADR_W: .res.b 2
RAM:FFFFF728 PHIOR_W: .res.b 2
RAM:FFFFF72A PHCR_W: .res.b 2
RAM:FFFFF72C PHDR_W: .res.b 2
RAM:FFFFF72E ADTRGR1_B: .res.b 1
RAM:FFFFF72F ADTRGR2_B: .res.b 1
RAM:FFFFF730 PBIOR_W: .res.b 2
RAM:FFFFF732 PBCRH_W: .res.b 2
RAM:FFFFF734 PBCRL_W: .res.b 2
RAM:FFFFF736 PBIR_W: .res.b 2
RAM:FFFFF738 PBDR_W: .res.b 2
RAM:FFFFF73A PCIOR_W: .res.b 2
RAM:FFFFF73C PCCR_W: .res.b 2
RAM:FFFFF73E PCDR_W: .res.b 2
RAM:FFFFF740 PDIOR_W: .res.b 2
RAM:FFFFF742 PDCRH_W: .res.b 2
RAM:FFFFF744 PDCRL_W: .res.b 2
RAM:FFFFF746 PDDR_W: .res.b 2
RAM:FFFFF748 PFIOR_W: .res.b 2
RAM:FFFFF74A PFCRH_W: .res.b 2
RAM:FFFFF74C PFCRL_W: .res.b 2
RAM:FFFFF74E PFDR_W: .res.b 2
RAM:FFFFF750 PEIOR_W: .res.b 2
RAM:FFFFF752 PECR_W: .res.b 2
RAM:FFFFF754 PEDR_W: .res.b 2
RAM:FFFFF756 PLIOR_W: .res.b 2
RAM:FFFFF758 PLCRH_W: .res.b 2
RAM:FFFFF75A PLCRL_W: .res.b 2
RAM:FFFFF75C PLIR_W: .res.b 2
RAM:FFFFF75E PLDR_W: .res.b 2
RAM:FFFFF760 PGIOR_W: .res.b 2
RAM:FFFFF762 PGCR_W: .res.b 2
RAM:FFFFF764 PGDR_W: .res.b 2
RAM:FFFFF766 PJIOR_W: .res.b 2
RAM:FFFFF768 PJCRH_W: .res.b 2
RAM:FFFFF76A PJCRL_W: .res.b 2
RAM:FFFFF76C PJDR_W: .res.b 2
RAM:FFFFF76E ADTRG0_B: .res.b 2
RAM:FFFFF770 PKIOR_W: .res.b 2
RAM:FFFFF772 PKCRH_W: .res.b 2
RAM:FFFFF774 PKCRL_W: .res.b 2
RAM:FFFFF776 PKIR_W: .res.b 2
RAM:FFFFF778 PKDR_W: .res.b 2
RAM:FFFFF77A .res.b 1
RAM:FFFFF77B .res.b 1
RAM:FFFFF77C .res.b 1
RAM:FFFFF77D .res.b 1
RAM:FFFFF77E .res.b 1
RAM:FFFFF77F .res.b 1
RAM:FFFFF780 PAPR_W: .res.b 2
RAM:FFFFF782 PBPR_W: .res.b 2
RAM:FFFFF784 PDPR_W: .res.b 2
RAM:FFFFF786 PJPR_W: .res.b 2
RAM:FFFFF788 PLPR_W: .res.b 2
RAM:FFFFF78A .res.b h'36
RAM:FFFFF7C0 HUDI_SDIR_W: .res.b 2
RAM:FFFFF7C2 HUDI_SDSR_W: .res.b 2
RAM:FFFFF7C4 HUDI_SDDRH_W: .res.b 2
RAM:FFFFF7C6 HUDI_SDDRL_W: .res.b 2
RAM:FFFFF7C8 .res.b h'38
RAM:FFFFF800 ADDR0H_B: .res.b 1
RAM:FFFFF801 ADDR0L_B: .res.b 1
RAM:FFFFF802 ADDR1H_B: .res.b 1
RAM:FFFFF803 ADDR1L_B: .res.b 1
RAM:FFFFF804 ADDR2H_B: .res.b 1
RAM:FFFFF805 ADDR2L_B: .res.b 1
RAM:FFFFF806 ADDR3H_B: .res.b 1
RAM:FFFFF807 ADDR3L_B: .res.b 1
RAM:FFFFF808 ADDR4H_B: .res.b 1
RAM:FFFFF809 ADDR4L_B: .res.b 1
RAM:FFFFF80A ADDR5H_B: .res.b 1
RAM:FFFFF80B ADDR5L_B: .res.b 1
RAM:FFFFF80C ADDR6H_B: .res.b 1
RAM:FFFFF80D ADDR6L_B: .res.b 1
RAM:FFFFF80E ADDR7H_B: .res.b 1
RAM:FFFFF80F ADDR7L_B: .res.b 1
RAM:FFFFF810 ADDR8H_B: .res.b 1
RAM:FFFFF811 ADDR8L_B: .res.b 1
RAM:FFFFF812 ADDR9H_B: .res.b 1
RAM:FFFFF813 ADDR9L_B: .res.b 1
RAM:FFFFF814 ADDR10H_B: .res.b 1
RAM:FFFFF815 ADDR10L_B: .res.b 1
RAM:FFFFF816 ADDR11H_B: .res.b 1
RAM:FFFFF817 ADDR11L_B: .res.b 1
RAM:FFFFF818 ADCSR0_B: .res.b 1
RAM:FFFFF819 ADCR0_B: .res.b 1
RAM:FFFFF81A .res.b 1
RAM:FFFFF81B .res.b 1
RAM:FFFFF81C .res.b 1
RAM:FFFFF81D .res.b 1
RAM:FFFFF81E .res.b 1
RAM:FFFFF81F .res.b 1
RAM:FFFFF820 ADDR12H_B: .res.b 1
RAM:FFFFF821 ADDR12L_B: .res.b 1
RAM:FFFFF822 ADDR13H_B: .res.b 1
RAM:FFFFF823 ADDR13L_B: .res.b 1
RAM:FFFFF824 ADDR14H_B: .res.b 1
RAM:FFFFF825 ADDR14L_B: .res.b 1
RAM:FFFFF826 ADDR15H_B: .res.b 1
RAM:FFFFF827 ADDR15L_B: .res.b 1
RAM:FFFFF828 ADDR16H_B: .res.b 1
RAM:FFFFF829 ADDR16L_B: .res.b 1
RAM:FFFFF82A ADDR17H_B: .res.b 1
RAM:FFFFF82B ADDR17L_B: .res.b 1
RAM:FFFFF82C ADDR18H_B: .res.b 1
RAM:FFFFF82D ADDR18L_B: .res.b 1
RAM:FFFFF82E ADDR19H_B: .res.b 1
RAM:FFFFF82F ADDR19L_B: .res.b 1
RAM:FFFFF830 ADDR20H_B: .res.b 1
RAM:FFFFF831 ADDR20L_B: .res.b 1
RAM:FFFFF832 ADDR21H_B: .res.b 1
RAM:FFFFF833 ADDR21L_B: .res.b 1
RAM:FFFFF834 ADDR22H_B: .res.b 1
RAM:FFFFF835 ADDR22L_B: .res.b 1
RAM:FFFFF836 ADDR23H_B: .res.b 1
RAM:FFFFF837 ADDR23L_B: .res.b 1
RAM:FFFFF838 ADCSR1_B: .res.b 1
RAM:FFFFF839 ADCR1_B: .res.b 1
RAM:FFFFF83A .res.b 1
RAM:FFFFF83B .res.b 1
RAM:FFFFF83C .res.b 1
RAM:FFFFF83D .res.b 1
RAM:FFFFF83E .res.b 1
RAM:FFFFF83F .res.b 1
RAM:FFFFF840 ADDR24H_B: .res.b 1
RAM:FFFFF841 ADDR24L_B: .res.b 1
RAM:FFFFF842 ADDR25H_B: .res.b 1
RAM:FFFFF843 ADDR25L_B: .res.b 1
RAM:FFFFF844 ADDR26H_B: .res.b 1
RAM:FFFFF845 ADDR26L_B: .res.b 1
RAM:FFFFF846 ADDR27H_B: .res.b 1
RAM:FFFFF847 ADDR27L_B: .res.b 1
RAM:FFFFF848 ADDR28H_B: .res.b 1
RAM:FFFFF849 ADDR28L_B: .res.b 1
RAM:FFFFF84A ADDR29H_B: .res.b 1
RAM:FFFFF84B ADDR29L_B: .res.b 1
RAM:FFFFF84C ADDR30H_B: .res.b 1
RAM:FFFFF84D ADDR30L_B: .res.b 1
RAM:FFFFF84E ADDR31H_B: .res.b 1
RAM:FFFFF84F ADDR31L_B: .res.b 1
RAM:FFFFF850 .res.b 1
RAM:FFFFF851 .res.b 1
RAM:FFFFF852 .res.b 1
RAM:FFFFF853 .res.b 1
RAM:FFFFF854 .res.b 1
RAM:FFFFF855 .res.b 1
RAM:FFFFF856 .res.b 1
RAM:FFFFF857 .res.b 1
RAM:FFFFF858 ADCSR2_B: .res.b 1
RAM:FFFFF859 ADCR2_B: .res.b 1
RAM:FFFFF85A .res.b 1
RAM:FFFFF85B .res.b 1
RAM:FFFFF85C .res.b 1
RAM:FFFFF85D .res.b 1
RAM:FFFFF85E .res.b 1
RAM:FFFFF85F .res.b 1
RAM:FFFFF860 MTAD_CNT0_W: .res.b 2
RAM:FFFFF862 MTAD_CYLR0_W: .res.b 2
RAM:FFFFF864 MTAD_DR0A_W: .res.b 2
RAM:FFFFF866 MTAD_DR0B_W: .res.b 2
RAM:FFFFF868 MTAD_GR0A_W: .res.b 2
RAM:FFFFF86A MTAD_GR0B_W: .res.b 2
RAM:FFFFF86C MTAD_TCR0_B: .res.b 1
RAM:FFFFF86D MTAD_TSR0_B: .res.b 1
RAM:FFFFF86E MTAD_TIER0_B: .res.b 1
RAM:FFFFF86F .res.b 1
RAM:FFFFF870 MTAD_CNT1_W: .res.b 2
RAM:FFFFF872 MTAD_CYLR1_W: .res.b 2
RAM:FFFFF874 MTAD_DR1A_W: .res.b 2
RAM:FFFFF876 MTAD_DR1B_W: .res.b 2
RAM:FFFFF878 MTAD_GR1A_W: .res.b 2
RAM:FFFFF87A MTAD_GR1B_W: .res.b 2
RAM:FFFFF87C MTAD_TCR1_B: .res.b 1
RAM:FFFFF87D MTAD_TSR1_B: .res.b 1
RAM:FFFFF87E MTAD_TIER1_B: .res.b 1
RAM:FFFFF87F .res.b h'381
RAM:FFFFFC00 SSU_SSCRH_0_B: .res.b 1
RAM:FFFFFC01 SSU_SSCRL_0_B: .res.b 1
RAM:FFFFFC02 SSU_SSMR_0_B: .res.b 1
RAM:FFFFFC03 SSU_SSER_0_B: .res.b 1
RAM:FFFFFC04 SSU_SSTDR0_0_B: .res.b 1
RAM:FFFFFC05 SSU_SSTDR1_0_B: .res.b 1
RAM:FFFFFC06 SSU_SSTDR2_0_B: .res.b 1
RAM:FFFFFC07 SSU_SSTDR3_0_B: .res.b 1
RAM:FFFFFC08 SSU_SSRDR0_0_B: .res.b 1
RAM:FFFFFC09 SSU_SSRDR1_0_B: .res.b 1
RAM:FFFFFC0A SSU_SSRDR2_0_B: .res.b 1
RAM:FFFFFC0B SSU_SSRDR3_0_B: .res.b 1
RAM:FFFFFC0C SSU_SSSR_0_B: .res.b 1
RAM:FFFFFC0D .res.b 3
RAM:FFFFFC10 SSU_SSCRH_1_B: .res.b 1
RAM:FFFFFC11 SSU_SSCRL_1_B: .res.b 1
RAM:FFFFFC12 SSU_SSMR_1_B: .res.b 1
RAM:FFFFFC13 SSU_SSER_1_B: .res.b 1
RAM:FFFFFC14 SSU_SSTDR0_1_B: .res.b 1
RAM:FFFFFC15 SSU_SSTDR1_1_B: .res.b 1
RAM:FFFFFC16 SSU_SSTDR2_1_B: .res.b 1
RAM:FFFFFC17 SSU_SSTDR3_1_B: .res.b 1
RAM:FFFFFC18 SSU_SSRDR0_1_B: .res.b 1
RAM:FFFFFC19 SSU_SSRDR1_1_B: .res.b 1
RAM:FFFFFC1A SSU_SSRDR2_1_B: .res.b 1
RAM:FFFFFC1A
RAM:FFFFFC1A .en

The IO pins come from the locations marked: P?IOR_W where ? is the port identifier A-L

You need to track down the routines that read those ports and convert the data read to the various SSM switch bits. Like I said, I've not spent any time on IO ports.

Yes no problem if that's on ADC ports, it's still interesting. Cause as you see, i find not link beetween theses adresses (I/O or anyone else) and the code (no Xref).
Maybe it's due to the way of loading these adresses (word xxxx instead of dword FFFFxxxx)
Thanks

I think i have to analyse this code: